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Art of Analog IC Design Workshop
Home
Workshop Introduction
1.1 Introduction to the Workshop
1.2 Introduction to PDKs
1.3 Introduction to the Digital Design Flow
1.4 Introduction to the Analog Design Flow
1.5 Introduction to the Semiconductor Ecosystem
Basic Models
2.1 Resistor
2.2 Capacitor
2.3 Inductor
2.4 Diode
2.5 BJT
2.6 MOSFET
Analog IC Design Flow
3.1 Analog IC Design Flow
3.2 OSIC-TOOLS
3.3 IIC-OSIC tools
IHP SG13G2 PDK
4.1 IHP’s SG13G2 130nm CMOS Technology
4.2 IHP’s SG13G2 MOSFETs
4.3 Device Characterization
Inverter Design Flow
5.1 Design Phase
5.2 Simulation Phase
5.3 Layout Phase
5.4 Post-Layout Verification Phase
CMOS Process Technology
6.1 Process Fabrication Technology
6.2 Modern Fabrication Flow
6.3 Modern Chip Packaging
PLL Case Study
7.1 What are oscillators?
7.2 PLL design flow
7.3 Analog measurements with AD3
7.4 Tiny Tapeout
Course Outline
SkillSurf Homepage
Inverter Design Flow
5.4 Post-Layout Verification Phase
5.4 Post-Layout Verification Phase
Table of contents
Step 3 - Inverter Verification & Parasitic Extraction in Magic VLSI for IHP SG13G2 130nm PDK
Step 4 - Inverter Post Layout Simulation in Xschem for IHP SG13G2 130nm PDK
Step 3 - Inverter Verification & Parasitic Extraction in Magic VLSI for IHP SG13G2 130nm PDK
Step 4 - Inverter Post Layout Simulation in Xschem for IHP SG13G2 130nm PDK
